| HomeFacultyElectricalEngineeringJoycee M. Mekie |
Joycee M. Mekie
Assistant Professor |
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B.E.: M. S. University of Baroda, 1997
M.E.: M. S. University of Baroda, 1999
Ph.D.: IIT Bombay, 2009
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Email: joycee @ iitgn.ac.in
Phone: :+91-79-23972324
Fax: +91-79-23972622 |
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| Research Interest
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- VLSI Design
- Asynchronous circuit design
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| Work Experience |
- Assistant Professor, Indian Institute of Technology, Gandhinagar, (Dec. 2009– present)
- Assistant Professor, Electrical Engg. Dept. M. S. University of Baroda, (Jun-2007 to Dec-2009)
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| Selected Recent Publications
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- S. Chakraborty, J. Mekie and D. K. Sharma, March 2006, "Reasoning about Synchronization using Abstract Timing Diagrams," in Special Issue on Formal Methods for Globally Asynchronous Locally Synchronous (GALS) Systems, Formal Methods in System Design (FMSD), pp. 153-169, Vol. 28, No. 2.
- J. Mekie, S. Chakraborty, G. Venkataramani, P. Thiagarajan and D. K. Sharma, March 2006, "Interface Design for Rationally Clocked GALS Systems," in Proc. of ASYNC, pp. 160-171.
- J. Mekie, S. Chakraborty and D. K. Sharma, Jan 2004, "Evaluation of Pausible Clocking Scheme for Interfacing High Speed IP Cores in GALS Framework," in Proc. of International Conference on VLSI Design, pp. 559-564.
- S. Chakraborty, J. Mekie and D. K. Sharma, Sept 2003, "Reasoning about Synchronization Issues in GALS Systems: A Unified Approach," invited paper in Proc. of Workshop on Formal Methods in GALS Architectures (FMGALS), Formal Methods Europe Symposium.
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